A low-complexity rate-compatible LDPC decoder

In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture (PLDA) is employed to reduce chip area and improve the throughput. Simulation results show that the proposed punctured codes have comparable error correcting performances with the performances of dedicated codes from WiMax standard. The decoder is implemented on the platform of Xilinx XC2V8000. Compared with previous WiMax LDPC decoders synthesized by the same device, our low-complexity decoder consumes less FPGA resources: reduction of slices by 63%, flip-flops by 73%, look-up tables (LUTs) by 60% and RAMs by 30%.