An 800 MHz 0.35 μm CMOS clock tree and PLL based on a new charge-pump circuit

Author

Orcioni, Simone ; Conti, Massimo ; Turchetti, Claudio ; Centorame, Angelo

Author_Institution

Dipt. di Elettronica e Autom., Ancona Univ., Italy

Volume

2

fYear

2002

fDate

2002

Firstpage

571

Abstract

The paper presents the design of an 800 MHz PLL implemented in a 0.35 μm CMOS technology. A novel charge pump circuit has been introduced in order to increase the frequency range of the PLL. A clock tree with buffers in the internal nodes has been designed for a chip of dimensions 1 cm×1 cm. The PLL supports internal to external clock frequency ratios of 1, 2, 4 and 8. PLL and clock tree have been used for power reduction by clock domain partitioning.

Keywords

CMOS integrated circuits; circuit simulation; clocks; integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; 0.35 micron; 1 cm; 800 MHz; CMOS clock tree/PLL; CMOS technology; PLL frequency range; charge pump circuit; chip dimensions; clock domain partitioning; clock tree buffers; external clock frequency ratios; internal nodes; power reduction; CMOS technology; Charge pumps; Circuits; Clocks; Energy consumption; Frequency conversion; Phase detection; Phase locked loops; Signal generators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046230

Filename

1046230