Impact of device variability in the communication structures for future synchronous SoC designs

In this paper we undertake a first step towards the study of the impact random dopant fluctuation (RDF) in the devices will have on on-chip synchronous communication structures, such as line drivers, repeaters and latches. The study is based on Monte Carlo simulation of the circuits at the 25, 18 and 13 nm technology generations using predictive device models. It has been found that variability has a significant impact on the performance of communication structures designed using small devices. Therefore, as a design methodology, it is proposed to use larger sized devices in critical parts of the circuits at the cost of larger area and power. Surprisingly, this work also points out that tapered buffers with larger tapering factor are more prone to delay variability, which might lead into reconsidering the optimal sizing of these structures. It may very well be possible to tackle such variabilities with active approaches, which are beyond the scope of this text.