Title :
VLSI architectures for median filtering with linear complexity
Author :
Lu, Erl-Huei ; Lee, Jau-Yien ; Yang, Yawpo
Author_Institution :
Dept. of Electr. Eng., Chang Gung Coll. of Med. & Technol., Tao-Yuan, Taiwan
Abstract :
Two hardware architectures for median filtering with linear complexity are presented. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock
Keywords :
VLSI; median filters; signal processing; smoothing methods; VLSI architectures; bit level architecture; filtered word; hardware architecture; high-speed signal processing; large window size; linear hardware complexity; median filtering; nonlinear signal smoothing; system clock; word level architecture; Buffer storage; Clocks; Educational institutions; Filtering; Hardware; Low pass filters; Nonlinear filters; Signal generators; Signal processing; Very large scale integration;
Conference_Titel :
TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-3679-8
DOI :
10.1109/TENCON.1996.608841
