A full adder implementation using SET based linear threshold gates

Author

Lageweg, Casper ; Cotofana, Sorin ; Vassiliadis, Stamatis

Author_Institution

Electr. Eng. Dept., Delft Univ. of Technol., Netherlands

Volume

2

fYear

2002

fDate

2002

Firstpage

665

Abstract

In this paper, we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction´s ability to control the transport of individual electrons. In particular, we present the implementation of a full adder using SET threshold gates. First, we augment the threshold gates with an active buffer in order to overcome feedback effects which can appear in passive SET networks. Second, we derive the circuit parameters for buffered SET threshold gates, and present the simulation results. Finally, we utilize the buffered threshold gates to build a full adder circuit, and verify the behavior of the resulting circuit via simulation.

Keywords

adders; buffer circuits; circuit simulation; integrated circuit design; integrated circuit modelling; logic design; logic simulation; single electron transistors; threshold logic; SET based linear threshold gates; SET tunnel junctions; active buffer circuits; full adders; individual electron transport control; passive SET network feedback effects; single electron tunneling devices; Adders; CMOS technology; Capacitance; Circuit simulation; Electrons; Feedback; Logic circuits; Switches; Threshold voltage; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046256

Filename

1046256