Title :
Increasing throughput of a RISC architecture using arithmetic data value speculation
Author :
Kelly, Daniel R. ; Phillips, Braden J. ; Al-Sarawi, Said
Author_Institution :
Centre for High Performance Integrated Technol. & Syst., Univ. of Adelaide, Adelaide, SA, Australia
Abstract :
Arithmetic data value speculation (ADVS) is a scheme to increase the throughput of a processor pipeline similar to conventional branch prediction. An approximate arithmetic unit, with an associated probability of correctness, provides an approximate result earlier than an exact unit, allowing the speculative issue of dependent operations. This paper investigates the performance gain in terms of retired instructions per clock (IPC) by employing ADVS in a RISC processor. Simulated results show the effect of probability of correctness and latency of approximate arithmetic units on IPC. In particular, minimum requirements for approximate arithmetic units are characterized, and maximum increase in IPC is shown for typical benchmark applications.
Keywords :
pipeline arithmetic; reduced instruction set computing; ADVS; RISC architecture; approximate arithmetic unit; arithmetic data value speculation; conventional branch prediction; correctness probability; instructions per clock; processor pipeline; Adders; Analytical models; Arithmetic; Clocks; Delay; Hardware; Pipelines; Reduced instruction set computing; Throughput; Timing;
Conference_Titel :
Signals, Systems and Computers, 2009 Conference Record of the Forty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-5825-7
DOI :
10.1109/ACSSC.2009.5470009
