DocumentCode :
2434790
Title :
HIPED: a tool for high-level power estimation of digital signal processing algorithms
Author :
Ben Dhaou, Imed ; Tenhunen, Hannu
Author_Institution :
Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
Volume :
2
fYear :
2002
fDate :
2002
Firstpage :
729
Abstract :
This paper describes HIPED, a tool for fast power estimation of DSP algorithms given its data-flow graph representation. Each node of the DFG is characterized for low-power using LP-DSM. In order to estimate the power consumption of the DSP, HIPED computes the entropy of the data transferred between two computational nodes. The entropy, which measures the data-activity of the circuit, is subsequently used by the power macro-model to predict the power consumption of the sink node. The total power consumption is thus obtained by summing up the power consumption of each node of the DFG. HIPED is used to estimate the power consumption of a variety of DSP algorithms used in typical wireless receivers implemented in 0.35 μm, 3.3 V CMOS process. The characterization process of arithmetic units implements both using SPL and CMOS circuit style showed that LP-DSM has lower prediction sum of error and lower error in cycle power than Gupta´s algorithm. Furthermore, the simulation results using real data showed that HIPED has a very good accuracy compared to circuit level power reported by PowerMill. The observed average error of our benchmark circuits is less than 10%.
Keywords :
CMOS integrated circuits; circuit CAD; circuit simulation; data flow graphs; digital signal processing chips; error analysis; high level synthesis; integrated circuit modelling; low-power electronics; radio receivers; software tools; 0.35 micron; 3.3 V; CMOS circuit style; CMOS process implementation; DFG node characterization; DSP; DSP algorithms; Gupta algorithm; HIPED tool; SPL circuit style; arithmetic units; benchmark circuits; cycle power error; data-flow graph representation; digital signal processing algorithms; high-level power estimation; power consumption; prediction error sum; simulation; sink node; transferred data entropy; wireless receiver; CMOS process; Circuits; Digital signal processing; Discrete wavelet transforms; Energy consumption; Image coding; Iterative algorithms; Libraries; Maximum likelihood decoding; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
Type :
conf
DOI :
10.1109/ICECS.2002.1046272
Filename :
1046272
Link To Document :
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