Analysis and comparison of low-voltage CML D-latch

In this work, a comparison between low-voltage and traditional CML D-latch implementation is carried out both in terms of delay and power-delay product. Different design strategies for high-speed or low-power are considered. The results show that the low-voltage D-latch has better speed and power-delay product when high speed is mandatory, but at the cost of an almost doubled power dissipation. However, the traditional implementation exhibits a better speed at a given bias current when low-power design is considered. The comparison is based on an analytical delay model of the topologies under investigation, which are shown to agree with SPICE simulations.