Synthesis of Pareto Efficient Technical Architectures for Multi-core Systems

In the area of embedded systems exists a continuous need for more computing power while still fulfilling a large set of constraints in - for instance - timing, safety, cost and energy consumption. Since single-core technologies seem to reach their limits, multi-core systems became the trend in this area. This paper describes a synthesis approach of application-specific homogeneous multi-core architectures, which are optimized towards timing, number of cores and energy consumption. Our method finds the optimal number of cores of the multi-processor system, along with the mapping of tasks onto these cores with the corresponding schedules and the frequency for each core. Since the optimization criteria are concurrent, the results are presented as a Pareto front. The approach is integrated in the model-based tooling framework, called Auto FOCUS3. As input our approach uses the information from the logical architecture of AF3, which represents a component based structure view of the system under development. The approach is based on the Branch & Bound algorithm, which was adapted for our three-dimensional optimization problem.