An effective memory-processor integrated architecture for computer vision

Author

Kim, Youngsik ; Han, Tack-Don ; Kim, Shin-Dug ; Yang, Sung-Bong

Author_Institution

Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea

fYear

1997

fDate

11-15 Aug 1997

Firstpage

266

Lastpage

269

Abstract

In this paper an effective memory-processor integrated architecture, called memory based processor array (MPA), for computer vision is proposed. The MPA can be easily attached into any host system via memory interface. In order to measure the impact of the memory interface structure an analytical model is derived. The performance improvement on the proposed model for the memory interface architecture of the MPA system can be 6%~40% for vision tasks consisting of sequential and data parallel tasks. The asymptotic time complexities of the mapping algorithms are evaluated to verify the cost-effectiveness and the efficiency of the MPA system

Keywords

computational complexity; computer vision; parallel architectures; performance evaluation; analytical model; asymptotic time complexities; computer vision; mapping algorithms; memory based processor array; memory interface architecture; memory-processor integrated architecture; performance improvement; Analytical models; Bandwidth; Computer architecture; Computer science; Computer vision; Decoding; Memory architecture; Parallel processing; Read-write memory; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing, 1997., Proceedings of the 1997 International Conference on

Conference_Location

Bloomington, IL

ISSN

0190-3918

Print_ISBN

0-8186-8108-X

Type

conf

DOI

10.1109/ICPP.1997.622654

Filename

622654