RRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs

Author

Eldredge, James G. ; Hutchings, Brad L.

Author_Institution

Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

Volume

4

fYear

1994

fDate

27 Jun-2 Jul 1994

Firstpage

2097

Abstract

Field programmable gate arrays (FPGAs) are an excellent technology for implementing neural networking hardware. This paper presents the run-time reconfiguration artificial neural network (RRANN). RRANN is a hardware implementation of the backpropagation algorithm that is extremely scalable and makes efficient use of FPGA resources. One key feature is RRANN´s ability to exploit parallelism in all stages of the backpropagation algorithm including the stage where errors are propagated backward through the network. This architecture has been designed and implemented on Xilinx XC3090 FPGAs, and its performance has been measured

Keywords

backpropagation; feedforward neural nets; field programmable gate arrays; neural chips; neural net architecture; parallel processing; reconfigurable architectures; Xilinx XC3090 FPGA; backpropagation algorithm; feedforward neural net; field programmable gate arrays; neural net architecture; parallel processing; run-time reconfiguration artificial neural network; Application software; Artificial neural networks; Backpropagation algorithms; Feeds; Field programmable gate arrays; Hardware; Neural networks; Neurons; Runtime; Speech;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-1901-X

Type

conf

DOI

10.1109/ICNN.1994.374538

Filename

374538