A H.264 decoder: A design style comparison case study

A comparison between an automated, and a semi-custom design, and synthesis of a H.264 restricted baseline profile decoder is the subject of this paper. The automated approach models the H.264 decoder as a Kahn Process Network (KPN), that is mapped on a multi-processor Field Programmable Gate Array (FPGA) execution platform. The semi-custom approach follows a BlueSpec design path, including Verilog code generation, compilation, and simulation, and the Xilinx Integrated Software Environment (ISE) tool chain for Xilinx Vertex-II FPGA synthesis. There is still a gap between automated and partially handcrafted design times, even when performance and cost parameters are otherwise comparable, and even when obvious limitations are avoided in both approaches. The purpose of the case study presented here is to pinpoint limitations and challenges when trying to close the gap.