An adaptive, CMOS neural array for pattern association

The authors report on the design, simulation and training of a CMOS synthetic neural array for pattern association. The circuit architecture is functionally equivalent to theoretical neural network models, but limited interconnection between layers is used to reduce interconnection densities to VLSI-implementable levels. Simulations of the limited-interconnect architecture demonstrate its ability to replicate a small set of desired neuromorphic behaviors. An analog cell and chip architecture for a 512-element, feedforward neural IC are described. Schematics are presented which illustrate fundamental design considerations.<>