A full adder based methodology for scaling operation in residue number system

Author

Soudris, D. ; Dasygenis, M. ; Mitroglou, K. ; Tatas, K. ; Thanailakis, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

Volume

3

fYear

2002

fDate

2002

Firstpage

891

Abstract

A systematic methodology for designing full-adder-based architectures in residue number system for scaling operation and its software tool development, are introduced. Starting from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. The proposed tool was implemented in C++ language and it is available for PC and HP platforms. The derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.

Keywords

C++ language; adders; hardware description languages; logic CAD; residue number systems; scaling circuits; C++ language; RNS; VHDL description; full adder based methodology; hardware complexity; residue number system; scaling operation; software tool development; throughput rates; Adders; Computer architecture; Design methodology; Digital signal processing; Dynamic range; Hardware; Parallel processing; Real time systems; Throughput; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046391

Filename

1046391