On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model

Author

Shen, Y.-N. ; Chen, X.T. ; Horiguchi, S. ; Lombardi, F.

Author_Institution

Actel Corp., Sunnyvale, CA, USA

fYear

1997

fDate

11-15 Aug 1997

Firstpage

350

Lastpage

353

Abstract

This paper presents new results for diagnosing (detection and location) multistage interconnection networks (MINs) in the presence of multiple faults. Initially, it is proved that the lower bound in the number of tests for multiple fault diagnosis (independent of the assumed fault model for the MIN) is 2×log₂N, where N is the number of inputs/outputs of the network. A new fault model is introduced; this fault model is applicable to interconnection networks implemented using CMOS technology. The characterization for diagnosing stuck-open faults is presented

Keywords

fault tolerant computing; multistage interconnection networks; CMOS fault model; CMOS technology; fault diagnosis; interconnection networks; lower bound; multiple fault diagnosis; multistage interconnection networks; stuck-open faults; CMOS technology; Computer science; Fault detection; Fault diagnosis; Information science; Multiprocessor interconnection networks; Semiconductor device modeling; Testing; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing, 1997., Proceedings of the 1997 International Conference on

Conference_Location

Bloomington, IL

ISSN

0190-3918

Print_ISBN

0-8186-8108-X

Type

conf

DOI

10.1109/ICPP.1997.622666

Filename

622666