DocumentCode
2437171
Title
Pipeline architecture for two-dimensional discrete cosine transform and its inverse
Author
Takala, Jarmo ; Nikara, Jari ; Punkka, Konsta
Author_Institution
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Volume
3
fYear
2002
fDate
2002
Firstpage
947
Abstract
In this paper, a pipeline architecture supporting both 8 × 8 discrete cosine transform (DCT) and its inverse is described. A regular two-dimensional algorithm with perfect shuffle topology for DCT is derived. The resulting signal flow graph is mapped vertically onto sequential processing units. A similar pipeline architecture is derived for the inverse transform. The unified architecture is obtained by mapping both previous pipelines onto common resources. The proposed architecture contains three multipliers for 8 × 8 transforms and its throughput can be increased with additional pipelining.
Keywords
computer architecture; digital signal processing chips; discrete cosine transforms; pipeline processing; signal flow graphs; IDCT; SFG mapping; discrete cosine transform; inverse DCT; inverse transform; multipliers; perfect shuffle topology; pipeline architecture; regular two-dimensional algorithm; sequential processing units; signal flow graph; unified architecture; Arithmetic; Computer architecture; Discrete cosine transforms; Discrete transforms; Parallel architectures; Pipeline processing; Signal processing; Throughput; Topology; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN
0-7803-7596-3
Type
conf
DOI
10.1109/ICECS.2002.1046405
Filename
1046405
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