Designing effective scan compression solutions for industrial circuits

With chip designs continuously shrinking nodes and new fault models evolving for lower nodes, scan compression based testing has become the standard test methodology. There are many papers on the implementation of Scan Compression. All these papers discuss the implementation of the technology in an idealistic environment. In this paper we present design issues that impact the overall scan compression architecture. This paper is an example of an industrial environment and the decisions that impact scan compression. Results of the implementation are presented with data.