Resource constrained clock recovery on programmable logic devices

Clock recovery is an important task in communications. With the usage of programmable logic devices as core elements in communication systems, the integration of clock recovery in programmable logic devices (PLDs) is highly desirable. This paper discusses some facilities being provided in recent families of PLDs for timing management, and shows new architectures oriented for the implementation of clock recovery circuits for high-speed communications using these facilities, in such a resource constrained environment. In particular, a 155 Mbps clock recovery unit using low cost Xilinx devices is discussed, and its performance is compared with more traditional methods.