DocumentCode
2437903
Title
AC IO loopback design for high speed μprocessor IO test
Author
Provost, Benoit ; Huang, Tiffany ; Lim, Chee How ; Tian, Kathy ; Bashir, Mo ; Atha, Mubeen ; Muhtaroglu, Ali ; Zhao, Cangsang ; Muljono, Harry
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
23
Lastpage
30
Abstract
This work presents the next generation AC IO loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low implementation costs apply to both.
Keywords
computer architecture; high-speed integrated circuits; integrated circuit design; integrated circuit testing; jitter; microprocessor chips; 20 ps; 50 ps; 800 MHz; AC IO loopback design; I/O defects; Intel processor architecture; bus architecture; high speed microprocessor IO test; jitter; AC generators; Bandwidth; Clocks; Costs; Delay; Jitter; Latches; Microprocessors; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1386933
Filename
1386933
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