DocumentCode
2437940
Title
An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor
Author
Wu, David M. ; Lin, Mike ; Reddy, Madhukar ; Jaber, Talal ; Sabbavarapu, Anil ; Thatcher, Larry
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
38
Lastpage
47
Abstract
This work describes an optimized DFT architecture and its implementation strategy for an Intel high performance (>3 GHz) microprocessor. Major DFT features and ATPG techniques implemented are described and key results are presented to show the return-on-investments (ROI) in the high volume manufacturing (HVM) test environments.
Keywords
automatic test pattern generation; design for testability; integrated circuit design; integrated circuit testing; microprocessor chips; ATPG techniques; DFT architecture; Intel high performance microprocessor; high volume manufacturing test environment; return on investment; test pattern generation; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Design for disassembly; Design for testability; Logic testing; Microprocessors; Silicon; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1386935
Filename
1386935
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