Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency

Asynchronous circuits do not have the clock-related issues as in their synchronous counterparts, thereby enabling further design tradeoffs and in-operation adaptive adjustments for energy efficiency. This paper introduces the framework of a parallel delay-insensitive asynchronous platform implementing adaptive dynamic voltage scaling (DVS), which is based on the observation of system fullness and workload prediction. The voltage reference generator and the voltage regulator have been integrated with the Finite Impulse Response (FIR) cores using the IBM 130nm 8RF process. Results show that the platform exhibits energy savings across various input workload scenarios.