Analysis of transconductances at all levels of inversion in deep submicron CMOS

Author

Bucher, Matthias ; Kazazis, Dimitrios ; Krummenacher, François ; Binkley, David ; Foty, Daniel ; Papananos, Yannis

Author_Institution

Nat. Tech. Univ. of Athens, Greece

Volume

3

fYear

2002

fDate

2002

Firstpage

1183

Abstract

This paper presents an in-depth analysis of transconductances in CMOS for advanced analog IC design. Transconductances in a 0.25 μm CMOS technology have been measured over a large range of geometries and bias conditions. Gate (g_mg), source (g_ms), drain (g_md) and bulk (g_mb) transconductances are consistently normalized and represented vs. inversion coefficient (IC) from very weak to moderate and strong inversion. The ideal transconductance behavior in particular in weak inversion is analyzed via the analytical structure of the EKV MOSFET model. The new EKV 3.0 MOSFET model shows excellent abilities to correctly represent transconductances at all levels of inversion and channel lengths.

Keywords

CMOS analogue integrated circuits; MOSFET; circuit CAD; integrated circuit design; integrated circuit modelling; semiconductor device measurement; semiconductor device models; 0.25 micron; CMOS analog IC design; EKV MOSFET model; MOSFET geometry/bias conditions; MOSFET inversion transconductance analysis; channel lengths; ideal transconductance behavior; inversion coefficient; inversion levels; moderate inversion; normalized gate/source/drain/bulk transconductances; strong inversion; transconductance measurement; very weak inversion; Analog integrated circuits; CMOS technology; Length measurement; MOS devices; MOSFET circuits; Performance analysis; Semiconductor device modeling; Silicon; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046464

Filename

1046464