• DocumentCode
    2438272
  • Title

    Case study: MOSFET instability due to charging of remnant stringers from a disposable polysilicon spacer process

  • Author

    Miller, James W. ; Hegedus, Homer L. ; Kaushik, Vidya

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1994
  • fDate
    16-19 Oct 1994
  • Firstpage
    145
  • Abstract
    Incompletely etched polysilicon “stringers” can produce a wide range of failure mechanisms in advanced integrated circuits. Parasitic leakage paths are often the direct cause of failures, but stringers can also form unwanted implant masks, or even act as the conducting channels of parasitic thin film transistors. A failure analysis case study was presented in which remnant stringers from a disposable polysilicon LDD spacer process led to large scale product fallout during burn-in. As a first step in the investigation, a series of circuit and transistor level stress experiments were performed. These produced evidence of significant transistor instability as the likely failure mechanism. Next a detailed Cross-section Transmission Electron Microscopy (XTEM) analysis was performed in order to relate the microstructure of the transistors to the observed electrical performance. The XTEM images clearly showed very small (30-70 nm) remnant polysilicon stringers at the edge of the gate poly reoxidation, above the transistor source/drain regions. The stringers were attributed to incomplete removal of the sidewall spacer polysilicon. This was confirmed by XTEM images of devices pulled from the fab before spacer etch. Finally, additional transistor electrical tests were performed to prove that these stringers acted as parasitic floating gates, gradually charging under saturation bias conditions. It was shown that this trapped charge, located just above the drain region, had a profound effect on subsequent device operation
  • Keywords
    MOSFET; electron microscopy; failure analysis; semiconductor device reliability; stability; transmission electron microscopy; LDD spacer process; MOSFET instability; cross-section TEM analysis; disposable polysilicon spacer process; electrical performance; failure analysis; parasitic floating gates; parasitic leakage paths; remnant stringer charging; saturation bias conditions; transistor instability; transmission electron microscopy; trapped charge; Etching; Failure analysis; Implants; Large-scale systems; MOSFET circuits; Microstructure; Performance analysis; Stress; Thin film transistors; Transmission electron microscopy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop, 1994. Final Report., 1994 International
  • Conference_Location
    Lake Tahoe, CA
  • Print_ISBN
    0-7803-1908-7
  • Type

    conf

  • DOI
    10.1109/IRWS.1994.515845
  • Filename
    515845