A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement

This paper proposes a low area calibration technique for TDC using a variable clock generator for accurate on-line delay measurement. For proposed calibration, we choose a sensitizable path whose end point is connected to TDC. Next we sensitize the path multiple times using a variable clock generator to apply the time intervals to TDC one by one. The TDC measures the time intervals one by one. From the obtained measurement results we can estimate the effects of process variation and aging on measurement results of TDC, and thus we can get accurate on-line delay measurement result and accurate failure prediction. Because the technique does not require extra circuits, except the variable clock generator and the two 2-to-1 switches, the area cost of the proposed calibration is low. In addition, the proposed calibration technique can be applied to not only basic monotonic TDCs, but also TDCs of different architecture such as ring oscillator-based ones. Experimental results confirm that the error of calibration depends on the resolution of the used variable clock generator. Area overhead is 9.6 %, which is 169.6 % smaller than the conventional stochastic calibration.