A critical path selection method for delay testing

Author

Padmanaban, Saravanan ; Tragoudas, Spyros

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

232

Lastpage

241

Abstract

An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS´85, ISCAS´89 and ITC´99 benchmarks.

Keywords

decision diagrams; integrated circuit testing; iterative methods; ISCAS85 benchmarks; ISCAS89 benchmarks; ITC99 benchmarks; critical path selection method; decision diagrams; delay testing; iterative methods; path delay faults; path intensive circuits; untestable faults; Benchmark testing; Circuit faults; Circuit testing; Delay effects; Integrated circuit interconnections; Manufacturing; Power supplies; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386957

Filename

1386957

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2438389