Practical application of a wafer level reliability qualification

Deficiencies in the traditional approach to ensuring product reliability (e.g. package level testing) were first noted way back in the early 1970´s. However, it was not until the late 1980´s to early 1990´s that WLRC was seriously considered and began to be implemented across the industry. This new approach for achieving greater levels of reliability required a fundamental change from the mind set of reliability verification on finished products (screening the outputs) to comprehending and controlling the various factors that determine reliability (controlling the inputs). This mind set is known as “building-in” or “designing-in” reliability and envisions a total reliability assurance and improvement strategy that is executed at all stages of semiconductor manufacturing. To meet the challenge of continuous improvement, it is now a corporate policy that a WLRC program be required at all R&D and production facilities with the intention of determining and eliminating all faults at their source of origin. Emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology and controlling production once technology has been transferred to the wafer fab. The description, philosophy and issues of integrating the WLRC program into a manufacturing environment have been described previously. Here a practical application is presented. As an example, the development, execution and results of a WLR qualification and production control plan for an advanced, submicron, triple-level metal CMOS process is provided