Automatic linearity (IP3) test with built-in pattern generator and analyzer

Author

Dai, Foster ; Stroud, Charles ; Yang, Dayu ; Qi, Shying

Author_Institution

Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

271

Lastpage

280

Abstract

We present a built-in self-test (BIST) approach based on direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. Of particular interest, and a main contribution of This work, is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) test using DDS. The approach described in This work has been implemented in Verilog and synthesized into FPGAs where it was used for functional testing and compared to simulation results.

Keywords

amplifiers; analogue integrated circuits; automatic test pattern generation; built-in self test; circuit simulation; direct digital synthesis; field programmable gate arrays; hardware description languages; integrated circuit testing; mixed analogue-digital integrated circuits; BIST; DDS; FPGA; Verilog; amplifier linearity test; analog circuit testing; automatic linearity test; built-in pattern analyzer; built-in pattern generator; built-in self test; direct digital synthesizer; functional testing; mixed signal systems; third order intermodulation product; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Hardware; Linearity; Pattern analysis; Synthesizers; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386961

Filename

1386961