An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs

This paper proposes an effective model for evaluating vertical signal propagation delay in through silicon via (TSV) based three-dimensional integrated circuits (3-D ICs). The capacitance model for on-chip interconnects is also proposed. All parasitic parameter values for an entire structure can be calculated by the closed-form equations. The delay model is constructed with the first- or second-order function of each parameter that obtained from a typical structure. The results obtained by the on-chip interconnect capacitance and delay models are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating an effect of process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.