Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC for a power gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power gating strategy that optimizes the inrush current profile, subject to the voltage-drop constraints. Our power gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve an average wake-up time reduction of 28% for all cases with our adaptive power gating method that exploits location (or layer) information of the aggressors in a 3D IC.