DocumentCode :
243865
Title :
Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis
Author :
Nikitin, Nikita ; Jahre, Magnus
Author_Institution :
Dept. of Comput. & Inf. Sci., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
172
Lastpage :
177
Abstract :
The imminent limitations imposed by the utilizationwall phenomenon compel architects to introduce heterogeneity in on-chip systems. The existing approaches to system-level synthesis of chip multiprocessors (CMPs) typically ignore physical aspects, leading to degradation in efficiency during later design stages. In this work, we propose and study the concept of patterned heterogeneous CMPs to handle the complexity of synthesis and extenuate the severity of physical aspects in post-synthesis engineering. A patterned CMP is a variation of a tiled architecture, in which layout regularity is enforced by fixing the tile size. Nevertheless, individual tiles may be implemented with different patterns, enabling a parameterizable degree of heterogeneity, which we leverage for synthesis efficiency. The results of synthesis demonstrate the effectiveness of patterned heterogeneity, suggesting it as a powerful tool for mastering the complexity of future on-chip systems.
Keywords :
integrated circuit layout; multiprocessing systems; network synthesis; chip multiprocessors; layout regularity; patterned heterogeneous CMPs; regularity-driven system-level synthesis; Complexity theory; Delays; Multicore processing; Silicon; System-on-chip; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.68
Filename :
6903355
Link To Document :
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