A holistic parallel and hierarchical approach towards design-for-test

Author

Ravikumar, C.P. ; Hetherington, G.

Author_Institution

Texas Instrum., Bangalore, India

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

345

Lastpage

354

Abstract

While design-for-test methods such as scan, ATPG, and memory BIST are now well established for ASIC products, their run-time for multi-million gate designs has become a problem. Too often, a tape-out is held up because pattern generation and verification are incomplete. This work describes a holistic design-for-test approach which exploits both hierarchy and parallelism on every aspect of the DFT to minimize the run-time impact.

Keywords

application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; logic gates; ASIC products; ATPG; DFT; design for test; hierarchical approach; holistic parallel approach; memory BIST; multimillion gate designs; pattern generation; pattern verification; run time impact minimization; Application specific integrated circuits; Automatic test pattern generation; Built-in self-test; Design engineering; Design for testability; Design methodology; Instruments; Manufacturing; Runtime; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1386970

Filename

1386970

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2438678