Title :
Minimizing power consumption in scan testing: pattern generation and DFT techniques
Author :
Butler, Kenneth M. ; Saxena, Jayashree ; Jain, Atul ; Fryars, Tony ; Lewis, Jack ; Hetherington, Graham
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; low-power electronics; power consumption; ATPG; DFT techniques; IC testing; at-speed testing; minimum operating voltages; pattern generation; power consumption minimization; scan testing; Clocks; Design for testability; Energy consumption; Instruments; Lifting equipment; Logic testing; Power demand; Power generation; Production; Test pattern generators;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1386971
