Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.