Title :
Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond Test
Author :
Kele Shen ; Dong Xiang ; Zhou Jiang
Author_Institution :
Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
Abstract :
Three-dimensional (3D) SoC is becoming one of the most promising approaches for extending Moore´s Law. However, managing test optimized scheme to reduce the cost of 3D SoCs is a significant challenge. In this paper, we propose a cost-effective optimized scheme of 3D SoCs for pre-bond test based on a generic cost model we defined. Both test time and number of TSV are considered in our novel scheme. Experimental results on ITC´02 SoC benchmark circuits show that our scheme is superior to one baseline solution and can effectively achieve good performance on test optimization.
Keywords :
benchmark testing; circuit optimisation; integrated circuit interconnections; integrated circuit testing; system-on-chip; three-dimensional integrated circuits; ITC´02 SoC benchmark circuits; TSV-based 3D SoC; cost-effective test optimized scheme; prebond test; system-on-chip; through-silicon-vias; IEEE Computer Society; Very large scale integration; 3D SoC; DfT; optimization; test access mechanism (TAM); test cost;
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
DOI :
10.1109/ISVLSI.2014.57
