DocumentCode :
243881
Title :
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression
Author :
Janfaza, Vahid ; Behnam, Payman ; Forouzandeh, Bahjat ; Alizadeh, Behrooz
Author_Institution :
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
220
Lastpage :
225
Abstract :
Long test application time for a System on Chip (SoC) is a major problem in digital design testing. This problem mostly originates from large test data. High volume test data not only increases required ATE memory and bandwidth, but also increases test time. Test compression reduces test data volume without any impact on its coverage. This work proposes two novel efficient test data compression schemes. These schemes suggest a slice partitioning along with a multiple dictionaries bitmask approach, and also a slice bit reordering method. These approaches are combined with low power method to decrease power consumption without sacrificing compression efficiency. Experimental results show improvements in compression efficiency and power consumption when compared with the existing works.
Keywords :
integrated circuit design; integrated circuit testing; low-power electronics; system-on-chip; compression efficiency; digital design testing; low-power enhanced bitmask-dictionary scheme; multiple dictionaries bitmask approach; power consumption; slice bit reordering method; slice partitioning; system on chip; test data compression; Dictionaries; Encoding; Hardware; Indexes; Switches; Test data compression; Vectors; bitmask; dictionary; low power scan testing; test compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.103
Filename :
6903363
Link To Document :
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