A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives

High permittivity materials have considered as a key enabler in nano-scaled underlap devices to achieve better electrostatic control. However, the enhanced fringing capacitance inherently associated with high-k materials poses several design challenges that limits its usage in high-performance (HP) circuits applications. To simultaneously improve the device and circuit performance, dual-k architecture had been proposed in terms of symmetric and asymmetric architectures. For specific SRAM applications, both the symmetric (SymD-k) and asymmetric (AsymD-kS) architectures performed better than the conventional low-k and purely high-k devices. The performance improvement in AsymD-kS based SRAM cell is due to its asymmetric nature that helps in adjusting the pull-up (PR) and cell-ratio (CR). Contradictorily, the improvements in SymD-k cell are attributed to the enhanced electrostatic integrity that increases SNMs without affecting PR and CR. Therefore, an in-depth comparative analysis between symmetric and asymmetric dual-k spacer architectures are utmost required that helps in understanding their respective electrostatics and its influence on HP circuit/SRAM applications. For the first time, this paper distinguishes the competing effects of symmetric and asymmetric dual-k spacer structures.