FPGA implementation and analysis of a multilevel coded modulation scheme

The authors describe a multilevel coded modulation scheme that has been designed for being implemented on FPGA. The goal of the design is to obtain good performance while keeping decoding delay and computational complexity as low as possible. This goal is obtained by a two-level scheme, where the partition chain of the 8-dimensional Gosset lattice is associated to a combination of 16-ary convolutional and block codes, at the first and second level respectively. The motivations behind the design choices are illustrated and the implementation on FPGA is presented. The authors conclude by analyzing the performance of the system and by showing experimental results.