Mining developers´ communication to assess software quality: Promises, challenges, perils

Summary form only given. In the recent decades, power consumption of System on Chip (SoC) is getting more dominant and Through-Silicon Via (TSV) technology has emerged as a promising solution to enhance system integration at lower cost and reduce footprint. Powerful microprocessor and immense memory capability integrated in standard 2D IC enabled to improve IC performance by shrinking IC dimensions. Our research evaluates the impact of Through-Silicon Via (TSV) on 3D chip performance as well as power consumption and investigates to understand the optimum TSV dimension (i.e., diameter, height, etc…) for 3D IC fabrication. The key idea is using the physical and electrical modeling of TSV which considers the coupling effects as well as TSV-to-bulk silicon parameters in 3D circuitry. In addition, by combining the conventional metrics for planar IC technology with TSV modeling, several methodologies are developed to evaluate the 3D chip´s behavior with respect to interconnect and repeaters. For example, by exploiting 101-stage Ring Oscillator and 100-inverter chain into 3D IC, it can be said that the through silicon via brings substantial benefits on local interconnect layers by improving overall transmission speed and reducing power consumption. The results in our research show that by adopting TSV infusion we can both reduce the power dissipation of interconnect and improve overall performance up to 35% in 4-die stacking case. Like all ICs, the TSV based 3D stacked IC need to be analyzed for manufacturing process variation. Hence, we investigate the variation of TSV dimension and then propose the optimal shape of TSV for the best performance of 3D systems integration. From simultaneous Monte Carlo simulations of TSV height and diameter, we can conclude that for given specific pitch in 3D IC technology, TSV with a small diameter is best fo