Layout-Aware Selection of Trace Signals for Post-Silicon Debug

Post-silicon debug is widely acknowledged as a bottleneck in SoC design methodology. A major challenge during post-silicon debug is the limited observability of internal signals. Existing approaches try to select a small set of beneficial trace signals that can maximize observability. Unfortunately, these techniques do not consider design constraints such as routability of the selected signals or routing congestion. Therefore, in reality, it may not be possible to route the selected signals. We propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion. Our experimental results demonstrate that our proposed approach can select routing friendly trace signals with negligible impact on observability.