DocumentCode
243933
Title
Function Extraction from Arithmetic Bit-Level Circuits
Author
Ciesielski, Maciej ; Brown, Walter ; Duo Liu ; Rossi, Anna
Author_Institution
Univ. of Massachusetts, Amherst, MA, USA
fYear
2014
fDate
9-11 July 2014
Firstpage
356
Lastpage
361
Abstract
The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic function from the circuit is accomplished by transforming the expression at the primary outputs into an expression at the primary inputs. Experimental results show application of the method to certain classes of large arithmetic circuits.
Keywords
adders; digital arithmetic; integrated circuit modelling; integrated logic circuits; logic gates; polynomials; adders; algebraic techniques; arithmetic bit-level circuit; arithmetic function extraction; bit-level network; logic gates; network flow problem; polynomial function; Adders; Computational modeling; Integrated circuit modeling; Logic gates; Mathematical model; Polynomials; Formal verification; arithmetic circuits; arithmetic verification;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location
Tampa, FL
Print_ISBN
978-1-4799-3763-9
Type
conf
DOI
10.1109/ISVLSI.2014.43
Filename
6903389
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