Title :
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems
Author :
Lee, Dongwon ; Bhattacharyya, Shuvra S. ; Wolf, Wayne
Author_Institution :
Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Design methodologies and tools based on the synchronous dataflow (SDF) model of computation have proven useful for rapid prototyping and implementation of digital signal processing (DSP) applications on multiprocessor systems. One significant problem that arises when mapping applications onto such embedded multiprocessors is the memory wall problem, which is becoming increasingly dominant in multiprocessor environments. In this paper, to help alleviate the memory wall problem, we propose a novel, high-performance buffer mapping policy for SDF-represented DSP applications on multiprocessor systems that support the shared-memory programming model. The proposed policy exploits the bank concurrency of a DRAM main memory system according to the analysis of the major forms of parallelism. The throughput is measured on both synthetic and real benchmarks. The simulation results show that the pro-posed buffer mapping policy is very useful, especially in memory-intensive applications where the total execution time of computational tasks is relatively small compared to that of memory operations. The performance improvement produced by our method is generally attained at the cost of additional banks and decreased bank utilization.
Keywords :
DRAM chips; buffer storage; digital signal processing chips; shared memory systems; DRAM concurrency; bank concurrency; bank utilization; digital signal processing; high-performance buffer mapping; memory wall problem; memory-intensive applications; multiprocessor DSP systems; shared-memory programming model; synchronous dataflow model; Computational modeling; Concurrent computing; Costs; Design methodology; Digital signal processing; Multiprocessing systems; Parallel processing; Prototypes; Random access memory; Throughput; DRAM main memory; DSP multiprocessor systems; SDF; bank concurrency; buffer mapping;
Conference_Titel :
Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-0-7695-3690-3
DOI :
10.1109/RSP.2009.34