Title :
Interconnect delay testings of designs on programmable logic devices
Author :
Tahoori, Mehdi Baradaran ; Mitra, Subhasish
Author_Institution :
Dept. of ECE, Northeastern Univ., Boston, MA, USA
Abstract :
Very thorough interconnect delay testing technique for designs implemented on programmable logic devices, such as FPGAs, is presented (application-dependent test). The presented technique achieves 1) 100% robust path delay coverage on all the paths in the design, 2) 100% transition fault coverage, and 3) 100% TARO coverage, transition to all reachable primary outputs. The required number of test configurations is two or four depending on the structure of the design. An algorithmic approach to generate the test vectors and configurations is presented.
Keywords :
SRAM chips; delays; fault diagnosis; field programmable gate arrays; integrated circuit interconnections; logic testing; FPGA; SRAM chips; TARO coverage; algorithmic method; application dependent test; fault diagnosis; interconnect delay testing; programmable logic devices; robust path delay coverage; test configurations; test vectors; transition fault coverage; Circuit faults; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic testing; Multiprocessor interconnection networks; Programmable logic arrays; Programmable logic devices; Propagation delay; Robustness;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387001
