DocumentCode
2440661
Title
Cache performance of combinator graph reduction
Author
Koopman, Philip J., Jr. ; Lee, Peter ; Siewiorek, Daniel P.
Author_Institution
Harris Semicond., Melbourne, FL, USA
fYear
1990
fDate
12-15 Mar 1990
Firstpage
39
Lastpage
48
Abstract
The threaded Interpretive Graph Reduction Engine (TIGRE) was developed for the efficient reduction of combinator graphs in support of functional programming languages and other applications. Results are presented of cache simulations of the TIGRE graph reducer with the following parameters varied: cache size, cache organization, block size, associativity, replacement policy, write policy, and write allocation. As a check on these results, the simulations are compared to measured performance on real hardware. From the results of the simulation study, it is concluded that graph reduction in TIGRE has a very heavy dependence on a write-allocate strategy for good performance, and very high spatial and temporal locality
Keywords
buffer storage; functional programming; graph theory; high level languages; performance evaluation; associativity; block size; cache organization; cache size; combinator graph reduction; functional programming languages; performance; replacement policy; spatial locality; temporal locality; threaded Interpretive Graph Reduction Engine; write allocation; write policy; write-allocate strategy; Application software; Cache memory; Clocks; Computational modeling; Computer science; Contracts; Engines; Functional programming; Hardware; System buses;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Languages, 1990., International Conference on
Conference_Location
New Orleans, LA
Print_ISBN
0-8186-2036-6
Type
conf
DOI
10.1109/ICCL.1990.63759
Filename
63759
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