A practical baseline process for advanced CMOS devices research [sub-50 nm MOSFETs]

Author

Ponomarev, Y.V. ; Loo, J.J.G.P. ; Rittersma, Z.M. ; Lander, R.J.P. ; Hooker, J.C. ; Doornbos, G. ; Surdeanu, R. ; Cubaynes, F.N. ; Dachs, C.J.J. ; Kubicek, S. ; Henson, K. ; Lindsay, R.

Author_Institution

Philips Res. Leuven, Belgium

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

27

Lastpage

30

Abstract

A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device architectures (e.g., double-gate transistors, strained channels). We have optimized the process parameters and show that high-performance transistors can be realized, promising direct applicability of the results to future manufacturing.

Keywords

MOSFET; dielectric thin films; laser beam annealing; 50 nm; CMOS process; MOSFET integration; double-gate transistors; high-k dielectrics; laser thermal annealing; metal gates; raised source/drain; strained channels; ultra-shallow junctions; Annealing; Boron; CMOS process; Dielectric devices; Dielectric materials; High K dielectric materials; High-K gate dielectrics; MOSFETs; Production; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256802

Filename

1256802