DocumentCode :
2440852
Title :
New junction concepts for sub-50 nm CMOS transistors: slim spacers and Ni silicide
Author :
Muller, M. ; Froment, B. ; Carron, V. ; Beverina, A. ; Palla, R. ; Pantel, R. ; Morin, P. ; Charbuillet, C. ; Pouydebasque, A. ; Boeuf, F. ; Skotnicki, T.
Author_Institution :
Philips Semicond., Crolles, France
fYear :
2003
fDate :
16-18 Sept. 2003
Firstpage :
31
Lastpage :
34
Abstract :
In this paper, we evaluate the potential of two concepts aiming at the vertical and horizontal reengineering of the S/D junctions of sub-50 nm-CMOS transistors: slim S/D spacers and Ni silicide. We demonstrate the benefit of the lateral spacer size reduction in terms of device performance. For the junction silicidation with Ni, we find electrically equivalent results while the silicidation depth is reduced by 50% with respect to the Co reference. This will enable the use of shallower S/D junctions giving a maximum DIBL and SCE control - an approach, which is especially interesting in combination with slim spacers.
Keywords :
MOSFET; nickel compounds; semiconductor device measurement; 50 nm; CMOS transistor junctions; DIBL control; NiSi; SCE control; drain induced barrier lowering; junction silicidation depth; lateral spacer size reduction; semiconductor junction reengineering; short channel effect; slim spacers; Annealing; CMOS process; Etching; Fabrication; Geometrical optics; MOS devices; Silicidation; Silicides; Silicon; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
Type :
conf
DOI :
10.1109/ESSDERC.2003.1256803
Filename :
1256803
Link To Document :
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