Improved Vt and Ioff characteristics of NMOS transistors featuring ultra-shallow junctions obtained by plasma doping (PLAD)

Author

Pouydebasque, A. ; Müller, M. ; Boeuf, F. ; Lenoble, D. ; Lallemen, F. ; Grouillet, A. ; Halimaoui, A. ; El Farhane, R. ; Delille, D. ; Skotnicki, T.

Author_Institution

Philips Semicond., Crolles, France

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

35

Lastpage

38

Abstract

We present in this paper a detailed analysis of the electrical behaviour of NMOS transistors with gate lengths down to Lg = 30 nm where the source/drain extensions (SDE) were developed using ultra low energy implantation (As 1 keV) or plasma doping (PLAD) at low bias (1.5 kV). PLAD splits show excellent threshold characteristics in comparison with As 1 keV: delayed Vt roll-down, reduced short channel effect (SCE) and drain induced barrier lowering (DIBL). The Ion/Ioff trade-off analysis reveals a much lower Ioff for comparable gate lengths when using PLAD instead of ULE. These behaviours are explained by a reduced junction depth Xj, which is confirmed by a parameter extraction on transistor characteristics and by analytical modelling.

Keywords

MOSFET; plasma materials processing; semiconductor device models; semiconductor doping; MASTAR modelling; NMOS transistors; drain induced barrier lowering; parameter extraction; plasma doping; reduced junction depth; reduced short channel effect; threshold characteristics; ultralow energy implantation; ultrashallow junctions; variable gate length; Analytical models; Ash; Delay effects; Implants; MOSFETs; Microelectronics; Plasma properties; Research and development; Semiconductor device doping; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256804

Filename

1256804