Title :
ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration
Author :
Anderson, Warren R. ; Krakauer, David B.
Author_Institution :
Digital Equip. Corp., Shrewsbury, MA, USA
Abstract :
We demonstrate that NMOS transistors stacked in a cascode configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. Circuits for gate voltage modulation were added to ensure uniform finger triggering of the fully silicided device. Layout and circuit rules were developed to avoid parasitic breakdown paths.
Keywords :
MOSFET; electric breakdown; electrostatic discharge; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; protection; ESD protection; NMOS transistor stack; NMOS transistors; cascode configuration; circuit rules; gate voltage modulation circuits; layout rules; mixed-voltage I/O ICs; parasitic breakdown paths; robust ESD protection; silicide-blocked technologies; silicided device; silicided technologies; uniform finger triggering; Clamps; Electrostatic discharge; Fingers; Integrated circuit technology; MOS devices; MOSFETs; Power supplies; Protection; Robustness; Voltage;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998
Conference_Location :
Reno, NV, USA
Print_ISBN :
1-878303-91-0
DOI :
10.1109/EOSESD.1998.737022
