How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the ICs are in the normal operating condition. A cascode design is therefore proposed to safely apply the low voltage triggered SCR (LVTSCR) devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latch-up danger. Such cascoded LVTSCRs with a holding voltage greater than V/sub DD/ of an IC can provide CMOS ICs with effective component-level ESD protection but without being accidentally triggered by system-level overshooting or undershooting noise pulses.