A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

Author

Puvvada, Venugopal ; Duvvury, Charvaka

Author_Institution

Reliability Group, Texas Instrum. India Ltd., Bangalore, India

fYear

1998

fDate

6-8 Oct. 1998

Firstpage

104

Lastpage

110

Abstract

This paper presents the use of circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 0.6 /spl mu/m CMOS technology product chip. Simulation of the ESD current paths near the V/sub dd/ pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models. These simulations are used to suggest issues to be considered in design of protection circuits to avoid this type of internal ESD failure.

Keywords

CMOS integrated circuits; circuit simulation; electrostatic discharge; failure analysis; integrated circuit design; integrated circuit modelling; integrated circuit reliability; protection; 0.6 micron; CMOS technology product chip; ESD current paths; ESD failure; HBM failure; MOS snapback models; circuit simulations; design issues; electrostatic discharge; internal ESD failure; internal clock buffer; power pin protection strategy; protection circuit design; simulation; CMOS technology; Circuit simulation; Circuit testing; Clocks; Driver circuits; Electrostatic discharge; Instruments; Pins; Protection; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998

Conference_Location

Reno, NV, USA

Print_ISBN

1-878303-91-0

Type

conf

DOI

10.1109/EOSESD.1998.737027

Filename

737027