Gate isolation technology for compact poly-CMP embedded flash memories

Author

Slotboom, M. ; Goarin, P. ; Akil, Nader ; van Duuren, M. ; Demand, Marc ; Wouters, J.M.D. ; Beckx, S. ; Leray, P. ; Baertsb, C. ; Baerts, C. ; Heylen, Nancy ; Pollentier, I.

Author_Institution

Philips Res. Leuven, Belgium

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

159

Lastpage

162

Abstract

Downscaling the cell size of embedded flash memories is hampered by a minimum thickness of the tunnel oxide due to reliability constraints. The longer effective channel of the compact poly-CMP flash cell is beneficial for its scalability compared to a discrete two-transistor cell. This paper investigates the influence of the isolation spacer between the floating and access gates in the compact poly-CMP cell on read and leakage currents, programming and erasing characteristics and endurance. The effect of sidewall oxidation steps on the read current of the compact cell is also analysed. This has led to an improved scalable embedded compact poly-CMP flash cell aimed for the 90 nm CMOS generation and beyond.

Keywords

CMOS memory circuits; chemical mechanical polishing; flash memories; isolation technology; leakage currents; oxidation; 90 nm; CMOS; access gates; compact poly-CMP flash cell; endurance; erasing characteristics; floating gates; gate isolation technology; isolation spacer; leakage current; memory cell size; poly-CMP embedded flash memories; programming characteristics; read current; reliability constraints; scalable embedded flash cell; sidewall oxidation steps; tunnel oxide minimum thickness; Character generation; Cleaning; Etching; Flash memory; Isolation technology; Oxidation; Plasma applications; Polymers; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256835

Filename

1256835